The Peripheral Component Interconnect Special Interest Group (PCI-SIG) has recently unveiled version 0.7 of the PCIe 7.0 specifications for member evaluation, with a plan to finalize the full specifications by 2025.

PCI-SIG, the consortium responsible for defining standards for the interconnects that link motherboards with critical components such as top-tier GPUs, is dedicated to ensuring these connections can support ongoing hardware innovations without becoming performance bottlenecks. The group is on track to establish the PCIe 7.0 standards this year, maintaining its routine of introducing new versions every three years.

The upcoming PCIe 7.0 standard is set to double the performance threshold of its predecessor, PCIe 6.0, achieving a raw bit rate of 128GT/s. This increase will enable a bi-directional transfer rate of 512GB/s in a 16-lane (x16) configuration. Furthermore, it will continue to utilize the Pulse Amplitude Modulation with 4 levels (PAM4) signaling, first introduced in PCIe 6.0. This technology encodes two bits of data per clock cycle, effectively doubling the data rate compared to the technologies used in PCIe 4.0 and PCIe 5.0.

Last April, the draft specifications for PCIe 7.0 were at version 0.5, and there appear to be no significant changes in the latest 0.7 version. Should the PCI-SIG members agree on this current version, the organization could finalize and release the standard within the year.

However, the adoption of PCIe 7.0 in consumer products like SSDs and GPUs will not be immediate. For example, the PCIe 5.0 standards were set in 2019, but it took until 2023 for the first PCIe 5.0 SSDs to hit the market. Similarly, PCIe 6.0 was finalized in January 2022, and as of December 2023, it is still undergoing testing for interoperability.

In addition to these timelines, manufacturers face challenges such as managing higher operational temperatures brought on by faster transfer speeds. Intel is actively addressing this issue by developing a PCIe Cooling Driver for Linux, which moderates SSD bandwidth if temperatures rise excessively. Consequently, we can expect future internal components to increasingly require substantial heat sinks and active cooling solutions to maintain their performance levels.