At the recent IEEE International Electron Device Meeting (IEDM), TSMC unveiled new insights into its N2 (2nm-class) manufacturing technology. This next-generation node offers a significant 24 to 35% reduction in power usage or a 15% boost in performance at the same power level, along with a 1.15X increase in transistor density compared to its previous 3nm process. These improvements are largely due to TSMC’s adoption of the innovative gate-all-around (GAA) nanosheet transistors, combined with the N2 NanoFlex design-technology co-optimization feature and other upgrades presented at IEDM.

The introduction of gate-all-around nanosheet transistors provides engineers with the ability to fine-tune channel width, optimizing the balance between performance and power efficiency. Additionally, the N2 technology enhances this capability with the N2 NanoFlex DTCO, which allows for the development of compact cells that minimize area while maximizing power efficiency, or larger cells that are optimized for peak performance. This technology also features six distinct voltage threshold levels (6-Vt), spanning a 200mV range, achieved through TSMC’s third-generation dipole-based integration, which incorporates both n-type and p-type dipoles.

The advancements in N2 focus on not only enhancing transistor drive currents through improvements in sheet thickness, junctions, dopant activation, and stress engineering but also on reducing effective capacitance (Ceff) to lead the way in energy efficiency. These enhancements collectively result in I/CV speed improvements of approximately 70% and 110% for N-type and P-type nanosheet transistors, respectively.

When compared to FinFETs, the N2 nanosheet transistors show a remarkable enhancement in performance per watt, particularly at lower supply voltages ranging from 0.5V to 0.6V. Here, process and device optimizations have managed to increase clock speeds by about 20% and reduce standby power consumption by around 75% at 0.5V. The integration of N2 NanoFlex and multiple threshold voltage options further adds to the design flexibility, particularly for creating energy-efficient processors with high logic densities.

The new transistor architecture and DTCO benefits have also significantly impacted SRAM scalability, a challenge in recent advanced nodes. With N2, TSMC has achieved a groundbreaking 2nm SRAM density of approximately 38Mb/mm^2. In addition to achieving record SRAM densities, TSMC has also reduced power consumption. As GAA nanosheet transistors exhibit tighter threshold voltage variation (Vt-sigma), N2 manages to lower the minimum operational voltage (Vmin) by about 20mV for High Current (HC) macros and 30–35mV for High Density (HD) macros compared to previous FinFET designs. These improvements support stable SRAM read and write operations down to roughly 0.4V while maintaining high yields and reliability.

Beyond transistor updates, TSMC’s N2 employs entirely new middle-of-line (MoL), back-end-of-line (BEOL), and far-BEOL wiring solutions to decrease resistance by 20% and enhance performance efficiency. The MoL now uses barrier-free tungsten wiring, which cuts vertical gate contact (VG) resistance by 55% and raises the frequency of the ring oscillator by approximately 6.2%. Furthermore, the first metal layer (M1) is now processed in a single EUV exposure pass followed by one etch step (1P1E), simplifying the process, reducing the number of required masks, and boosting overall efficiency. TSMC states that employing EUV 1P1E for M1 reduces standard cell capacitance by nearly 10% and saves several EUV masks. Additionally, N2 reduces metal (My) and via (Vy) resistance by 10%.

Moreover, for high-performance computing (HPC) applications, N2 includes features like super high-performance MiM (SHP-MiM) capacitors that offer about 200fF/mm² of capacitance, facilitating higher maximum operating frequencies (Fmax) by minimizing transient voltage droop.

TSMC’s N2 technology also introduces a new Cu RDL option optimized for face-to-face and face-to-back 3D stacking with an SoIC bond pitch of 4.5 μm, which TSMC anticipates will be a key feature for AI, HPC, and mobile applications.

Production of TSMC’s N2 process technology is expected to commence in the second half of 2025.